Massively Parallel Architectures

Dr. Colin Egan, Department of Computer Science, University of Hertfordshire

Traditionally the memory wall problem, limiting processor performance, is overcome by introducing extra levels in the memory hierarchy. Unfortunately, this increases the design complexity and power consumption of the overall system. Integrating the processing logic and memory simplifies the system design, can reduce power consumption, and certainly reduces memory access times. This technique is termed Processing In Memory (PIM). Many PIMs can be connected together to form massively parallel cellular architectures. Our speaker will introduce us to this fascinating field.

Location

Steria Limited, Hemel Hempstead
Three Cherry Trees Lane, Hemel Hempstead, HP2 7AH

Cost

Free for members and non-members

Last updated 12th November, 2023 at 11:55am